The Dram-based Reconfigurable Acceleration Fabric (draf) Uses Commodity Dram Technology to Implement a Bit-level, Reconfigurable Fabric That Improves Area Density by 10 times and Power Consumption by More Than

......The end of Dennard scaling has made it imperative to turn toward applicationand domain-specific acceleration as an energy-efficient way to improve performance. Field-programmable gate arrays (FPGAs) have become a prominent acceleration platform as they achieve a good balance between flexibility and efficiency. FPGAs have enabled accelerator designs for numerous domains, including datacenter computing, in which applications are much more complex and change frequently, and multitenancy sharing is a principal way to achieve resource efficiency. For FPGA-based accelerators to become widely adopted, their cost must remain low. This is an issue both for large-scale datacenters that are optimized for total cost of ownership and for small mobile devices that have strict budgets for power and chip area. Unfortunately, conventional FPGAs realize arbitrary bit-level logic functions using static RAM (SRAM) based lookup tables and configurable interconnects, both of which incur significant area and power overheads. The poor logic density and high power consumption limit the functionality that one can implement within an FPGA. Previous research has used networks of medium-sized FPGAs or developed multicontext FPGAs to circumvent these limitations, but these approaches come with their own overheads. For details, see the sidebar, “FPGAs in Datacenters and Multicontext Reconfigurable Fabrics.” We developed the DRAM-Based Reconfigurable Acceleration Fabric (DRAF), a reconfigurable fabric that improves logic density and reduces power consumption through the use of dense, commodity DRAM arrays. DRAF is bit-level reconfigurable and has similar flexibility as conventional FPGAs. DRAF Mingyu Gao